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25G retimers in a 100G system with FCI & Xilinx

1,101 views · Published 31 January 2014 · 2:48 · Indexed 30 September 2026

Channel: Texas Instruments · 2014 · Science & Technology

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This 100G system demonstration features TI's 25 Gbps retimer interoperability with FCI's ExaMAX ™ connectors and a Xilinx Virtex-7 FPGA 25/28G transceiver.  The demo shows a Xilinx Virtex-7 FPGA generating four lanes of 25.78125 Gbps of data using a PRBS31 pattern, which feeds into a standard backplane configuration with FCI's ExaMAX connector, which then feeds into TI's 25G retimer evaluation board. The retimer equalizes, retimes and re-transmits this data back into the FPGA with zero error rate. TI's 25G retimer helps solve real world problems of sending data over a standard backplane.

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