VHDL6526 update waffle - hazards, synchronous design and internal buses

250 views · Published 30 October 2017 · 20:02 · Indexed 5 October 2026

Channel: bwack · 2017 · Science & Technology

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Continuing developing on the C64 CIA IC vhdl design (VHDL6526) based on datasheet description. It's the end of the day. This video is like a worklog for today. Talking about bad coding style for FPGA: logics on the clock network. non synchronous design, and the fact that FPGAs does not have internal tri-state signals.

https://github.com/bwack/VHDL6526

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