HDL Verifier: FPGA Data Capture
3,572 views · Published 24 April 2017 · 4:10 · Indexed 6 November 2026
Channel: MATLAB · 2017 · Science & Technology
See what's new in the latest release of MATLAB and Simulink: https://goo.gl/3MdQK1 Download a trial: https://goo.gl/PSa78r Prototyping a design on an FPGA enables high-speed processing of real-world input, but debugging when problems occur is extremely difficult due to the lack of visibility of internal signals. FPGA Data Capture in HDL Verifier™ enables you to define signals in the FPGA to probe, and automatically generates the components needed to connect your FPGA board to MATLAB® or Simulink® to analyze signals. See this capability in action, together with Logic Analyzer, using an audio design example.
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