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Archive: Rethinking Interconnect for High-Performance Computer Systems

1,019 views · Published 12 July 2010 · 55:58 · Indexed 21 September 2026

Channel: UW Video · 2010 · Education

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Over the past several decades, the ongoing miniaturization of silicon circuits has completely transformed the power and performance space of VLSI systems. Continued performance improvements may prove elusive, however, as both gate speed scaling and Moore's Law scaling slow down. Exacerbating these trends is the worsening bottleneck of chip-to-chip communication, driven by the growing disparity in size and power between off-chip and on-chip wiring. Ronald Ho of Stanford University and Sun Microsystems shares how researchers at Sun Labs are addressing these problems by dramatically reducing the costs of off-chip communication, allowing them to tile together multiple chips to create large "virtually monolithic" integrated circuits. The basic communication technology is one formed via the close positioning of two chips. This so-called "Proximity Communication" can use either capacitive coupling or optical communication.
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